1. Technical Field
The present invention relates to ferroelectric memories and methods for manufacturing the same.
2. Related Art
As a ferroelectric memory having a stacked structure, a structure in which a plug is connected to one of selection transistors, a ferroelectric capacitor is formed on the plug, another plug is connected to the other of the selection transistors, and a bit line is formed on the other plug is known. Each of the plugs connected to each of the bit lines is disposed between adjacent ones of the ferroelectric capacitors, such that arrangement and fabrication of the plugs would become very difficult with further miniaturization and higher density arrangement of capacitors. Also, further device miniaturization may cause the manufacturing process to become more complicated, for example, because the plugs and the bit lines are formed separately from one another in the ferroelectric memory described above, which requires mask positioning to be conducted with high accuracy. An example of related art is described in Japanese laid-open patent application JP A-2004-6563.